1. Field of the Invention
The present invention relates generally to a digital data communications system, and more specifically to an error control coding arrangement wherein convolutional codes transmitted over QAM or PSK digital channels, are decoded using a plurality of Viterbi decoders (for example).
2. Description of the Prior Art
In recent years, there has been an increasing demand for efficient and reliable digital data transmission. This demand has been accelerated by the emergence of large-scale, high-speed data networks for the exchange and processing of digital information in various fields.
It has been widely recognized that maximum likelihood decoding using Viterbi algorithms of convolutional codes, is an effective, attractive error correcting technique for a digital communications system. The hardware size of a Viterbi decoder increases with an increase in a constraint length (K) thereof. At present time, a Viterbi decoder with K=7 is practically used, and the maximum decoding speed thereof falls within a range from 15 Mbps (Mega bits per second) to 25 Mbps. It follows that an information transmission rate is limited by the maximum decoding speed.
In order to increase the information transmission rate, there has been proposed an error control arrangement which includes a plurality of convolutional encoders and a plurality of Viterbi decoders. Before turning to the present invention it is deemed advantageous to discuss such a prior art arrangement with reference to FIGS. 1 to 6.
As shown in FIG. 1, an information sequence D10 from a digital source (not shown), is applied to a serial-parallel (S/P) converter 10. The information sequence D10 is a bit sequence denoted by (B1, B2, B3, . . . , B6, . . . ) in FIG. 2. The converter 10 transforms the bit sequence D10 into two bit sequences D21 (B1, B3, B5, . . . ) and D22 (B2, B4, B6, . . . ) as shown in FIG. 2. A convolutional encoder 21, having a 1/2 conversion rate, is supplied with the bit sequence D21 and generates two encoded sequences D31, D32 which are applied to the next stage, viz., a parallel-serial (P/S) converter 31. The encoded sequence D31 is represented by (P1, P3, P5, . . . ) while the other encoded sequence D32 by (Q1, Q3, Q5, . . . ) in FIG. 2. Similarly, a convolutional encoder 22, having the same configuration as the encoder 21, receives the bit sequence D22 and generates two encoded sequences D33, D34 which are applied to a P/S converter 32. The encoded sequence D33 is represented by (P2, P4, P6, . . . ) while the other encoded sequence D34 by (Q2, Q4, Q6, . . . ) (FIG. 2). As is well known in the art, a convolutional encoder generally includes a plurality of shift registers for temporarily holding binary symbols and logical circuitry for producing the encoded sequences. A convolutional encoder itself is not directly concerned with the instant invention and hence further description thereof will be omitted for brevity. The two encoded sequences D31, D32 are combined into a bit sequence D43 (P1, Q1, P3, Q3, . . . ) by a P/S converter 31, while the two encoded sequences D33, D34 are transformed into a bit sequence D44 (P2, Q2, P4, Q4, . . . ). A QPSK (Quadriphase Shift Keying) modulator 40 modulates the two bit sequences D43, D44 applied thereto. The modulated signals are added to form the resultant QPSK signal which is transmitted over a channel.
The modulated signal is applied to a QPSK demodulator 50 which implements demodulation using a reproduced carrier (viz., reference signal) and outputs two received bit sequences D53, D54. It should be noted that the received bit sequences D53, D54 are not necessarily identical with the bit sequences D43, D44, respectively even if no transmission error exists. More specifically, the bits P1, P2 respectively included in the received sequences D53, D54, may take one of the following four combinations: (P1, P2), (/P2, P1), (/P1, /P2) and (P2, /P1) where a notation "/" denotes a phase shift of 90.degree..
It is assumed that the carrier is correctly reproduced at the receiving section including the demodulator 50 (viz., the phase of the reference signal is identical with that of the carrier). In this instance, the received bit sequences D53, D54 assume the configuration in FIG. 3, in which "r" attached to each of the received bits P1, P2, Q1, Q2, . . . indicates that the corresponding bit is corrupted by transmission error. An S/P converter 61 receives the bit sequence D53 and transforms same into two sequences D65, D66. Similarly, an S/P converter 62 is supplied with the other bit sequence D54 and transforms same into two sequences D67, D68. The sequences D65, D66 are inputted to a Viterbi decoder 71 and undergo maximum-likelihood decoding using the Viterbi algorithm. The Viterbi decoder 71 applies an output sequence D73 to a P/S converter 80. Similarly, the other Viterbi decoder 72 is supplied with the sequences D67, D68 and generates an output sequence D74 which is applied to the P/S converter 80. It is assumed that each of the Viterbi decoders 71, 72 has corrected the aforesaid transmission errors merely for the sake of simplifying the description. Accordingly, the character "r" indicating a transmission error is not attached to each bit of the sequences D73, D74. It is understood that a bit sequence D81 derived from the P/S converter 80 is a replica of the information sequence D10.
On the other hand, it is assumed that the carrier is incorrectly reproduced such that each of the orthogonal phases of the reference signal shifts from a reference phase by 90.degree.. In this case, the received bit sequences D53, D54 are as indicated in FIG. 4. The sequence D53 is transformed into two sequences D65, D66 by the S/P converter 71, while the sequence D54 is transformed into two sequences D67, D68. In the event that a so-called transparent code is used, each of the bit sequences D65-D66 and D67-D68 is arranged in a manner that each of the Viterbi decoders 71, 72 implements the normal operation on the data bits applied. The term "transparent code" implies that even if all of the codes applied to a Viterbi decoder are reversed, the Viterbi decoder is able to normally implement error correction. Consequently, the Viterbi decoder 71 applies the output sequence D73 to the P/S converter 80 to which the other bit sequence D74 is applied. Thus, the P/S converter 80 generate a bit sequence D81 which apparently differs from the original sequence D10.
FIG. 5 is a block diagram showing a second prior art technique. The arrangement of FIG. 5 differs from that of FIG. 1 in that: (a) the former arrangement further includes a P/S converter 31' and a S/P converter 61' and (b) a modulator 40' takes the form of BPSK (Binary PSK) and a demodulator 50' is arranged to demodulate the BPSK modulated signal applied thereto. FIG. 6 is a time chart of bit sequences appearing in the FIG. 5 arrangement.
The P/S converter 31' is provided to transform the two bit sequences D43, D44 into a sequence D95. The modulator 40' implements BPSK modulation using the sequence D95 and transmits the modulated signal to the demodulator 50' over the channel. The demodulator 50' recovers the modulating sequence D95 and applies the recovered sequence D96 to the S/P converter 61' which transforms the sequence D96 into two sequences D97, D98.
In the event that the S/P converter 61' correctly executes the serial-parallel conversion, then the sequences D97, D98 are respectively identical with the sequences D53, D54 as shown in FIG. 3. In this instance, the P/S converter 80 is able to output the replica of the original information sequence D10 as discussed in connection with FIG. 3.
However, assuming that the S/P converter 61' has failed to correctly implement the serial-parallel conversion and generated the bit sequences D97, D98 as shown in FIG. 6. The S/P converters 61, 62 respectively produce parallel sequences D65-D66 and D67-D68. In this instance, each of the Viterbi decoders 71, 72 is able to normally implement the error correcting operation. Accordingly, since the bit sequences D65-D66, D67-D68 of FIG. 6 correspond to the sequences D67-D68, D65-D66 of FIG. 3, there exists the probability that the resultant sequence derived from the P/S converter 80 will take the form of B2, B1, B4, B3, . . . (it is assumed that the Viterbi decoders 71, 72 have successfully removed transmission errors if any).